The invention relates to a method of frame decoding as and more particularly to such a method used in a signal transmission system having a frame structure with periodically occurring synchronizing information which marks the start of each frame.
Digital signal devices are being used to an increasing extent in transmission technology, in particular over radio relay links. For the additional transmission of information bits for service channel purposes and message purposes, such devices require a multiplexer-demultiplexer system with a so-called super-frame structure.
The publication "Multiplexers for 8.448 Mbit/s in Positive-Negative Stuffing Technology" by U. Assmus and others (see communication from the Research Institute of the FTZ of the German Post Office in Darmstadt, published in "Nachrichtentechnische Fachberichte" 42 (1972), page 245-256) states the following. The combination of a plurality of PCM basic systems to form a system of the second order for the more efficient transmission of digital signals over long distances will represent an effective preliminary stage of a digital network and can be fulfilled by multiplexers without transmission losses. As a synchronous digital network cannot be expected to exist in the near future, asynchronous multiplexers should be of significance for a long transition period. Amongst asynchronous multiplexers, the multiplexer featuring "positive-negative" stuffing technology appears to be of special significance. In the receiving component of the multiplexer-demultiplexer system. synchronism between transmitter and receiver is established in a synchronizing device. For this purpose, in a generally conventional manner, a periodically recurring synchronizing word is transmitted in the bit flow. The synchronizing word provides the bit flow with a frame structure, where the start of the frame is marked by the synchronizing word.
As stated in the description of the Siemens digital signal multiplex device DSMX8/34, a frame codeword consisting of 10 bits is used at the start of the pulse frame. In the frame synchronizing circuit a shift register is shifted relative to the bit flow until, via a logic-linking device, a frame codeword is recognized at the outputs of the shift register.